Conventional arithmetic logic circuits used for forward error correction and detection, communications, encoding and decoding and general bit manipulation using Galois field linear transformations may be implemented in hardware or software. In certain applications such as encryption and error control coding, it is necessary to perform arithmetic operations, e.g., add, subtract, square root, multiply, and divide over Galois fields. Any such operation between any two members in a Galois field will result in an output (sum, difference, square root, product, quotient) which is another value in the same Galois field. The number of elements in a Galois field is 2m where m is the degree of the field. For example, GF(24) would have sixteen different elements in it; GF(28) would have 256. A Galois field is generated from an irreducible polynomial in a particular power. Each Galois field of a particular degree will have a number of irreducible polynomials form each of which may be devised a different field using the same terms but in a different order.
Division over a Galois field is done by multiplying the dividend by the reciprocal of the divisor. This divisor reciprocal can be generated in a number of ways. One way is to have a stored look-up table of reciprocals where the divisor is the address for the table. One problem with this approach is that for each field of each irreducible polynomial there must be stored a separate table. In addition, the tables can only be accessed in serial: if parallel operations are required a copy of each table must be provided for each parallel operation. Another approach is to multiply each of the stored Galois field elements by the particular divisor. The value that produces a product of one is then the reciprocal of the particular divisor. Once again all of the values have to be stored and in multiple copies if parallel operation is contemplated. And, a Galois field multiplier is required just to accomplish the retrieval. A third approach uses two linear feedback shift registers (LFSR) each configured to generate a selected Galois field of a particular irreducible polynomial. The first is initialized to the divisor; the second is initialized to “1”. Starting from the divisor value the two are clocked synchronously. When the product of the first LFSR equals “1” the divisor has been multiplied by its reciprocal. The product of the second LFSR at that moment is the Galois field element that is the reciprocal of the divisor. One problem with this approach is that for each Galois field of each irreducible polynomial for each degree a different pair of LFSRs is required. In both, the second look-up table approach, above, and the LFSR approach the search for the reciprocal requires up to 2m−1 iterations.